Currently, CCD (Charge Coupled Device) is a primary solid image sensor device, and has advantages of low noise, large dynamic response range, high sensitiveness, etc. However, the CCD is disadvantageous due to its poor compatibility with dominant CMOS (Complementary Metal Oxide Semiconductor) technologies, that is, it is difficult to integrate CCD-based image sensor in a single chip. Due to the use of same CMOS technologies, CIS (COMS Image Sensor) can integrate array of pixels with peripheral circuit into a single chip. In comparison with the CCD, the CIS has advantages of small volume, light weight, low power consummation, easy programming and control, low cost, etc.
Dark current is one of the factors strongly influencing the CIS performance. For a semiconductor device, electron and hole are in a dynamic balance of generation, migration and combination at a temperature higher than absolute zero. The higher the temperature is, the higher the rate at which the electron and hole are generated and migrated is, and the larger the dark current is. Generally, the dark current is an amount of current released by photodiode without incident light, and it shall be zero for an ideal image sensor. However, the photodiode in each pixel acts as capacitor also, and when the capacitor releases charges slowly, a voltage of the dark current may be equivalent to the output voltage under weak incident light even without incident light. Consequently in such a case, an “image” on display can still be observed due to the release of charges accumulated by the capacitor. Therefore, how to optimize the fabrication of photodiode to reduce the dark current of CIS becomes a primary issue confronted by those skilled in the art.
The dark current may be increased by the following two reasons. One is a current formed by moveable charges on surface of the photodiode region, and the other is a damage to the surface of the photodiode region due to plasma etching process for forming poly-silicon gate and sidewall of MOS transistor; and the damage influences crystal structure of the surface on the semiconductor, and further influences the rate at which electron and hole are generated and migrated on the surface of the photodiode region, thus increasing the dark current of CIS.
As disclosed in Chinese Patent Application No. 200610030016, an oxide layer is formed on a semiconductor substrate to prevent plasma etching from damaging the surface of the semiconductor substrate. Referring to FIG. 1, an oxide layer 27 is formed in a region I of semiconductor substrate 21, i.e. a photodiode region, so that the damage to the surface of the semiconductor substrate 21 by the plasma etching can be reduced. Meanwhile, a good interface between the oxide layer 27 and the semiconductor substrate 21 can be realized to eliminate some charges at the interface of the semiconductor substrate. Unfortunately, a mask has to be added to form the oxide layer 27 in the photodiode region according to this patent application, thus increasing process cost.
As disclosed in U.S. Pat. No. 6,514,785, the dark current is reduced by pinning the surface of the photodiode. FIG. 2 is a diagram illustrating a structural of the pixel cell in CMOS image sensor formed in the prior art. Referring to FIG. 2, a semiconductor substrate 11 of, for example, p-type silicon, is divided into two regions: region I (photodiode region) and region II (MOS transistor region); a gate dielectric layer 14 is formed in the region II of the semiconductor substrate 11; a poly-silicon gate 13 is formed on the gate dielectric layer 14; lightly doped source/drain extension regions 18 are formed at both sides of the poly-silicon gate 13 in the region II of the semiconductor substrate 11; source/drain regions 15 are formed at both sides of the poly-silicon gate 13 in the region II of the semiconductor substrate 11; a deep doped n-type well 16 of the photodiode is formed in the region I of the semiconductor substrate 11, where the deep-doped n-type well 16 and the semiconductor substrate 11 constitute a PN junction forming the photodiode; a shallow doped p-type region 17 is formed in the region I of the semiconductor substrate 11 by ion implantation process, where the shallow doped p-type region 17 and the deep doped n-type well 16 of the photodiode constitute a PN junction forming a second diode; and PIN layer is formed on the surface of the semiconductor substrate 11 to pin moveable charges on the surface of the semiconductor substrate 11, thus reducing the dark current. Also the formation of the second diode requires an additional mask, resulting in an increased process cost.
The two methods mentioned above provide solutions for preventing the damage to the surface of the semiconductor substrate 21 caused by plasma etching and for pinning moveable charges on the surface of the semiconductor substrate 11 respectively, however, both of them require an additional mask. Integration of the solutions enables both reduction of the damage to the surface of the semiconductor substrate 211 caused by plasma etching and pinning of moveable charges on the surface of the semiconductor substrate 11, but two additional mask have to be added, thus increasing process steps and cost.